同步序列发生器设计VHDL代码Quartus仿真

名称：同步序列发生器设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

同步序列发生器

1、根据预定义的序列（01010111，可自定义），串行输出序列

2、根据计数器，按顺序依次输出串行序列

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.工程文件

2.程序文件

3.管脚分配

4.仿真测试文件

5.仿真图

输出为程序里预定义的序列01010111

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?Synchronous_sequence_lys?IS
???PORT?(
??????clk_lys????????????:?IN?STD_LOGIC;--输入50M
??????reset_n_lys????????:?IN?STD_LOGIC;--低电平复位
??????Sync_sequence_lys??:?OUT?STD_LOGIC--同步序列输出
???);
END?Synchronous_sequence_lys;
ARCHITECTURE?trans?OF?Synchronous_sequence_lys?IS
??--定义变量?
???SIGNAL?pre_sequence_lys??????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???
???SIGNAL?sequence_count_lys????:?STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"000";
???
???SIGNAL?Sync_sequence_lys_out?:?STD_LOGIC?:=?'0';
BEGIN
???PROCESS?(clk_lys)
???BEGIN
??????IF?(clk_lys'EVENT?AND?clk_lys?=?'1')?THEN
?????????IF?(reset_n_lys?=?'0')?THEN
????????????pre_sequence_lys?<=?"01010111";--预定义的序列，可修改为任意所需序列（8位）
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clk_lys)
???BEGIN
??????IF?(clk_lys'EVENT?AND?clk_lys?=?'1')?THEN
?????????IF?(reset_n_lys?=?'0')?THEN
????????????sequence_count_lys?<=?"000";
?????????ELSE
????????????sequence_count_lys?<=?sequence_count_lys?+?"001";--计数0~7，共8位
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clk_lys)
???BEGIN
??????IF?(clk_lys'EVENT?AND?clk_lys?=?'1')?THEN--同步时钟
?????????CASE?sequence_count_lys?IS--根据计数值，按顺序输出序列
????????????WHEN?"000"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(7);--第7位
????????????WHEN?"001"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(6);--第6位
????????????WHEN?"010"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(5);--第5位
????????????WHEN?"011"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(4);--第4位
????????????WHEN?"100"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(3);--第3位
????????????WHEN?"101"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(2);--第2位
????????????WHEN?"110"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(1);--第1位
????????????WHEN?"111"?=>
???????????????Sync_sequence_lys_out?<=?pre_sequence_lys(0);--第0位
????????????WHEN?OTHERS?=>
???????????????Sync_sequence_lys_out?<=?'0';
?????????END?CASE;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1274