FIFO设计（深度16，位宽为8）Verilog代码modelsim仿真

名称：FIFO设计（深度16，位宽为8）Verilog代码modelsim仿真

软件：modelsim

语言：Verilog

代码功能：

FIFO设计（深度16，位宽为8）

1、设计深度16，位宽为8的FIFO

2、支持输出almost_full,almost_empty

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 程序文件

2. Testbench文件

3. 仿真图

部分代码展示:

//fifo?16×8fifo
module?a_fifo
(
input?clk,
input?rst,
input?[7:0]?din,
input?wr_en,
input?rd_en,
output?reg?[7:0]?dout,
output?empty,
output?full,
output?almost_full,
output?almost_empty
);
reg?[7:0]?ram?[15:0];
reg?[6:0]?count=7'd0;
reg?[6:0]?rp=7'd0;
reg?[6:0]?wp=7'd0;
integer?i;
always@(posedge?clk)
if(rst)begin
wp<=7'd0;
rp<=7'd0;
dout<=8'd0;
count<=7'd0;
for(i=0;i<16;i=i+1)
ram[i]<=8'b00000000;
end
else
case({rd_en,wr_en})
2'b00:count<=count;
2'b01:
if(~full)begin
ram[wp]<=din;
if(wp>=7'd15)
wp<=7'd0;
else
wp<=wp+7'd1;
count<=count+7'd1;
rp<=rp;
end
2'b10:
if(~empty)begin
dout<=ram[rp];
if(rp>=7'd15)
rp<=7'd0;
else
rp<=rp+7'd1;
count<=count-7'd1;
end
2'b11:
if(empty)begin
ram[wp]<=din;
if(wp>=7'd15)
wp<=7'd0;
else
wp<=wp+7'd1;
count<=count+7'd1;
end
else?if(full)begin
dout<=ram[rp];
if(rp>=7'd15)
rp<=7'd0;
else
rp<=rp+7'd1;
count<=count-7'd1;
end
else?begin

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1122