A平方减1算法实现设计VHDL代码Quartus仿真

名称：A平方减1算法实现设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：A平方减1算法实现

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.工程文件

2.程序文件

3.程序运行

4.RTL图

5.Testbench

6.仿真图

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
USE?ieee.std_logic_unsigned.all;
ENTITY?squareA_subtract1?IS
???PORT?(
??????CLK???????:?IN?STD_LOGIC;
??????A?????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????CLR???????:?IN?STD_LOGIC;
??????LOAD??????:?IN?STD_LOGIC;
??????
??????Z?????????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0):=?"0000000000000001";
??????END_FLAG??:?OUT?STD_LOGIC:=?'0'
???);
END?squareA_subtract1;
ARCHITECTURE?square_1?OF?squareA_subtract1?IS
???SIGNAL?state??????????:?STD_LOGIC_VECTOR(1?DOWNTO?0)?:=?"00";
???SIGNAL?square_A?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000000000000001";
???SIGNAL?ADD_counter?????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000000000000000";??
???SIGNAL?multiplier_A?????:?STD_LOGIC_VECTOR(15?DOWNTO?0):=?"0000000000000000";
???SIGNAL?LOAD_DFF1?:?STD_LOGIC?:=?'0';
???SIGNAL?LOAD_DFF2?:?STD_LOGIC?:=?'0';
???SIGNAL?LOAD_fall??????:?STD_LOGIC:=?'0';
???SIGNAL?RA?????????????:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?unsigned_inputA??:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?END_FLAG_out?:?STD_LOGIC:=?'0';
BEGIN
???PROCESS?(CLK)
???BEGIN
??????IF?(CLK'EVENT?AND?CLK?=?'1')?THEN--将LOAD通过触发器打2拍
?????????LOAD_DFF1?<=?LOAD;
?????????LOAD_DFF2?<=?LOAD_DFF1;
??????END?IF;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1001