基于FPGA的数字电子时钟VHDL代码Quartus仿真

名称：基于FPGA的数字电子时钟VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

1)数字钟功能:能进行年、月、日、时、分、秒计时显示的数字电子钟；

2)校时功能:对年、月、日、时、分、秒进行手动调节以校准时间；

3)扩展功能:另外实现闹钟功能以及秒表功能。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 管脚分配

6. 仿真图

闹钟模块

年月日模块

时分秒模块

秒表模块

端口复用切换模块

按键输入模块

模式选择模块

显示模块

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--闹钟模块
ENTITY?alarm?IS
???PORT?(
??????clk???????????????:?IN?STD_LOGIC;
??????RST???????????????:?IN?STD_LOGIC;
??????
??????alarm_hour_add????:?IN?STD_LOGIC;
??????alarm_minute_add??:?IN?STD_LOGIC;
??????
??????alarm_hour_out????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????alarm_minute_out??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
???);
END?alarm;
ARCHITECTURE?behave?OF?alarm?IS
???
???SIGNAL?alarm_hour???:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?alarm_minute?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
BEGIN
???
???PROCESS?(clk,?RST)
???BEGIN
??????IF?(RST?=?'1')?THEN
?????????alarm_hour?<=?"00000000";
?????????alarm_minute?<=?"00000000";
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(alarm_hour_add?=?'1')?THEN
????????????IF?(alarm_hour?>=?"00010111")?THEN
???????????????alarm_hour?<=?"00000000";
????????????ELSE
???????????????alarm_hour?<=?alarm_hour?+?"00000001";
????????????END?IF;
?????????ELSIF?(alarm_minute_add?=?'1')?THEN
????????????IF?(alarm_minute?>=?"00111011")?THEN
???????????????alarm_minute?<=?"00000000";
????????????ELSE
???????????????alarm_minute?<=?alarm_minute?+?"00000001";
????????????END?IF;
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???
???alarm_hour_out?<=?alarm_hour;
???alarm_minute_out?<=?alarm_minute;
???
END?behave;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=714