基于FPGA的2PSK(BPSK)调制解调Verilog代码Quartus仿真

名称：基于FPGA的2PSK(BPSK)调制解调Verilog代码Quartus仿真

软件：Quartus

语言：Verilog

代码功能：基于FPGA的2PSK(BPSK)调制解调

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. Testbench

5. 仿真图

部分代码展示:

`timescale?1ns?/?1ps
//testbench
module?BPSK_tb;
//?Inputs
reg?clk;
reg?rst;
reg?data_in;
//?Outputs
wire?data_out;
parameter?delay_time=20*256;
//?Instantiate?the?Unit?Under?Test?(UUT)
BPSK_TOP?uut?(
.clk(clk),?
.rst(rst),?
.data_in(data_in),?
.data_out(data_out)
);
initial?begin
//?Initialize?Inputs
clk?=?0;
rst?=?0;
data_in?=?0;
//?Wait?100?ns?for?global?reset?to?finish
repeat?(100)?begin
#delay_time;
??????data_in?=?1;??
#delay_time;
data_in?=?0;?
#delay_time;
??????data_in?=?1;??
#delay_time;
data_in?=?1;
#delay_time;
??????data_in?=?1;??
#delay_time;
data_in?=?0;
#delay_time;
data_in?=?0;
#delay_time;
??????data_in?=?1;??
#delay_time;
data_in?=?0;
//?Add?stimulus?here
end
end
??????
always?begin
clk?=?0;
#10;
clk?=?1;
#10;
end
endmodule

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=630