SPI接口设计VHDL代码Quartus仿真

名称：SPI接口设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

SPI接口设计

SPI接口定义：要求地址位8bit，数据位16bit，再加上读写标识为1bit，一共25bit。

Bit顺序为：读写标识1bit+地址位8bi+数据位16bit。

本资源支持VHDL和Verilog两种语言。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 管脚分配

对应开发板位置：

4. 程序编译

5. RTL图

6. Testbench

7. 仿真图

SPI接口定义：要求地址位8bit，数据位16bit，再加上读写标识为1bit，一共25bit。Bit顺序为：读写标识1bit+地址位8bi+数据位16bit。

写数据仿真图

读数据仿真

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?SPI_top?IS
???PORT?(
??????sys_rst_p??:?IN?STD_LOGIC;--复位
??????sys_clk????:?IN?STD_LOGIC;--14.7456???
??????SPI_CLK????:?OUT?STD_LOGIC;--100K
??????SPI_DI?????:?OUT?STD_LOGIC;--MOSI
??????SPI_ENB????:?OUT?STD_LOGIC;--CS低电平有效
??????SPI_DO?????:?IN?STD_LOGIC--MISO
???);
END?SPI_top;
ARCHITECTURE?behave?OF?SPI_top?IS
???COMPONENT?spi_interface?IS
??????PORT?(
?????????sys_rst_p??:?IN?STD_LOGIC;
?????????sys_clk????:?IN?STD_LOGIC;
?????????SPI_CLK????:?OUT?STD_LOGIC;
?????????SPI_DI?????:?OUT?STD_LOGIC;
?????????SPI_ENB????:?OUT?STD_LOGIC;
?????????SPI_DO?????:?IN?STD_LOGIC;
?????????WR_RD_in???:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);
?????????int_wr_data_in?:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0);
?????????int_add_in?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????int_rd_data_out?:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)
??????);
???END?COMPONENT;
??????
???SIGNAL?WR_RD_in????????:?STD_LOGIC_VECTOR(1?DOWNTO?0);--读写寄存器--10=写,01=读
???SIGNAL?int_wr_data_in??:?STD_LOGIC_VECTOR(15?DOWNTO?0);
???SIGNAL?int_add_in??????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?int_rd_data_out?:?STD_LOGIC_VECTOR(15?DOWNTO?0);
BEGIN
???
???WR_RD_in?<=?"01";--10=写,01=读
???int_wr_data_in?<=?"0001001000110100";--数据
???int_add_in?<=?"01010110";--地址
???--调用SPI接口模块
???i_spi_interface?:?spi_interface
??????PORT?MAP?(
?????????sys_rst_p????????=>?sys_rst_p,
?????????sys_clk??????????=>?sys_clk,
?????????SPI_CLK??????????=>?SPI_CLK,
?????????SPI_DI???????????=>?SPI_DI,
?????????SPI_ENB??????????=>?SPI_ENB,
?????????SPI_DO???????????=>?SPI_DO,
?????????WR_RD_in?????????=>?WR_RD_in,
?????????int_wr_data_in???=>?int_wr_data_in,
?????????int_add_in???????=>?int_add_in,
?????????int_rd_data_out??=>?int_rd_data_out
??????);
???
END?behave;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=609