Verilog基础--ps/2键盘

libing64

在上一节多路数码管的基础上，适当修改，使之变成一个显示模块：

module mutiSeg7
(
CLK, RSTn, LED,select,data
);
input CLK, RSTn;
output [7:0] LED;
output [5:0] select;
input [7:0] data;//????????8λ????
reg [3:0] rLowData;
reg [3:0] rHighData;
reg [5:0]rEn = 6'b111_110;
parameter T1ms = 16'd50_000;
parameter _0 = 8'b1100_0000,
_1 = 8'b1111_1001,
_2 = 8'b1010_0100,
_3 = 8'b1011_0000,
_4 = 8'b1001_1001,
_5 = 8'b1001_0010,
_6 = 8'b1000_0010,
_7 = 8'b1111_1000,
_8 = 8'b1000_0000,
_9 = 8'b1001_0000,
_a = 8'b1000_1000,
_b = 8'b1000_0011,
_c = 8'b1100_0110,
_d = 8'b1010_0001,
_e = 8'b1000_0110,
_f = 8'b1000_1110;
//1ms
reg [31:0] count;
always @(posedge CLK or negedge RSTn)
if(!RSTn)
count <= 0;
else if (count == T1ms)
count <= 26'b0;
else count <= count + 26'b1;
//????????λ
always @(posedge CLK or negedge RSTn)
if(!RSTn)
begin
rLowData <= _0;
end
else
case(data[3:0])
0: rLowData <= _0;
1: rLowData <= _1;
2: rLowData <= _2;
3: rLowData <= _3;
4: rLowData <= _4;
5: rLowData <= _5;
6: rLowData <= _6;
7: rLowData <= _7;
8: rLowData <= _8;
9: rLowData <= _9;
10: rLowData <= _a;
11: rLowData <= _b;
12: rLowData <= _c;
13: rLowData <= _d;
14: rLowData <= _e;
15: rLowData <= _f;
default: rLowData <= _0;
endcase
//获取高四位
always @(posedge CLK or negedge RSTn)
if(!RSTn)
begin
rHighData <= _0;
end
else
case(data[7:4])
0: rHighData <= _0;
1: rHighData <= _1;
2: rHighData <= _2;
3: rHighData <= _3;
4: rHighData <= _4;
5: rHighData <= _5;
6: rHighData <= _6;
7: rHighData <= _7;
8: rHighData <= _8;
9: rHighData <= _9;
10: rHighData <= _a;
11: rHighData <= _b;
12: rHighData <= _c;
13: rHighData <= _d;
14: rHighData <= _e;
15: rHighData <= _f;
default: rLowData <= _0;
endcase
//获取低四位
reg[7:0] rLED;
always @(posedge CLK or negedge RSTn)
if(!RSTn)
rEn <= 6'b111_110;
else if(count == T1ms)
case(rEn)
6'b111_110:
begin
rEn <= 6'b111_101;
rLED <= rLowData;
end
6'b111_101:
begin
rEn <= 6'b111_110;
rLED <= rHighData;
end
default:
begin
rEn<= 6'b111_110;
rLED <= rHighData;
end
endcase
assign LED = rLED;
assign select = rEn;
endmodule

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PS2模块是参考某国外网站的，姑且可以认为是没问题的

module ps(pclk,pdata,scan_code,parity_error,rdy);
// Port declarations
input pclk; // PS_2 clock input
input pdata; // PS_2 pdata input
output[7:0] scan_code; // Scan_code output
output parity_error; // Parity output
output rdy; // pdata ready output
// Internal Variables
reg[9:0] register;
reg[3:0] counter;
reg parity_error, rdy;
assign scan_code = register[9:2];
assign parity = register[1];
// PS/2 logic
always @ (negedge pclk)
begin
register <= {register[8:0], pdata}; // receive pdata
if (counter == 4'b1011)
counter <= 4'b0000;
else
counter <= counter + 4'b1;
end
// PS/2 parity logic
always @ (posedge pclk)
begin
if (counter == 4'b1011)
if (!parity == ^scan_code) // parity check (odd parity)
rdy <= 1'b1;
else
parity_error <= 1'b1;
else // not all 10 bits receiverd yet
begin
rdy <= 1'b0;
parity_error <= 1'b0;
end
end
endmodule

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然后再写一个顶层模块

module top(
pclk,
pdata,
parity_error,
rdy,CLK,
RSTn,
LED,
select
);
input pclk; // PS_2 clock input
input pdata; // PS_2 pdata input
wire[7:0] scan_code; // Scan_code output
output parity_error; // Parity output
output rdy; // pdata ready output
ps P(
.pclk(pclk),
.pdata(pdata),
.scan_code(scan_code),
.parity_error(parity_error),
.rdy(rdy)
);
input CLK, RSTn;
output [7:0] LED;
output [5:0] select;
//input [7:0] data;//????????8λ????
mutiSeg7 seg
(
.CLK(CLK),
.RSTn(RSTn),
.LED(LED),
.select(select),
.data(scan_code)
);
endmodule

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现在显示结果并不符合ps/2协议，而且会显示H这种诡异的字母，正常按16进制显示只有0-9，a-f
有高手的话帮忙分析，分析，看看是什么问题？

libing64 · 发表于 2013-4-23 22:05:42

找了一晚上也没找出问题所在，真蛋碎

Verilog基础--ps/2键盘

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