library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602 is
?? Port ( Clk : in std_logic;?? --状态机时钟信号,同时也是液晶时钟信号,其周期应该满足液晶数据的建立时间
?? Reset:in std_logic;??
????????? LCD_RS : out std_logic; --寄存器选择信号
????????? LCD_RW : out std_logic; --液晶读写信号
????????? LCD_EN : out std_logic; --液晶时钟信号
??? LED???? : out std_logic;
????????? LCD_Data : out std_logic_vector(7 downto 0));?? --液晶数据信号
end LCD1602;
architecture Behavioral of LCD1602 is
?? type state is (set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,write_LCD_Data);
?? signal Current_State:state;
?? type ram2 is array(0 to 7) of std_logic_vector(7 downto 0);
constant cgram:ram2:=(
??? ("00001000"),
??? ("00001111"),
??? ("00010010"),
??? ("00001111"),
??? ("00001010"),
??? ("00011111"),
??? ("00000010"),
??? ("00000010"));--年字符数据存储器??????????????????????????
?? signal Clkk???? : std_logic;
?? signal Count??? : std_logic_vector(20 downto 0);
?? signal Clk_Out : std_logic;
?? signal LCD_Clk : std_logic;
begin
?? LCD_EN