Wiley集成电路新书 system integration【好书推荐】

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Wiley集成电路新书 system integration【好书推荐】
这本书叫system integration：From Transistor Design to Large Scale Integrated Circuits，由Wiley出版，书是高质量的PDF电子书，不是扫描版，
讲的很全，可以拿来用作工程应用参考书！！


Symbols xvii
1 Semiconductor Physics 1
1.1 Band Theory of Solids 1
1.2 Doped Semiconductor 5
1.3 Semiconductor in Equilibrium 7
1.3.1 Fermi–Dirac Distribution Function 7
1.3.2 Carrier Concentration at Equilibrium 10
1.3.3 Density Product at Equilibrium 11
1.3.4 Relationship between Energy, Voltage, and Electrical Field 15
1.4 Charge Transport 17
1.4.1 Drift Velocity 17
1.4.2 Drift Current 19
1.4.3 Diffusion Current 21
1.4.4 Continuity Equation 23
1.5 Non-Equilibrium Conditions 24
Problems 32
References 34
Further Reading 34
2 pn-Junction 35
2.1 Inhomogeneously Doped n-type Semiconductor 35
2.2 pn-Junction at Equilibrium 38
2.3 Biased pn-Junction 40
2.3.1 Density Product under Non-Equilibrium Conditions 40
2.3.2 Current–Voltage Relationship 44
2.3.3 Deviation from the Current–Voltage Relationship 46
2.3.4 Voltage Reference Point 48
2.4 Capacitance Characteristic 50
2.4.1 Depletion Capacitance 50
2.4.2 Diffusion Capacitance 55
2.5 Switching Characteristic 59
2.6 Junction Breakdown 61
2.7 Modeling the pn-Junction 64
2.7.1 Diode Model for CAD Applications 64
2.7.2 Diode Model for Static Calculations 66
2.7.3 Diode Model for Small-Signal Calculations 68
Problems 69
References 71
3 Bipolar Transistor 73
3.1 Bipolar Technologies 73
3.2 Transistor Operation 83
3.2.1 Current–Voltage Relationship 84
3.2.2 Transistor under Reverse Biased Condition 92
3.2.3 Voltage Saturation 93
3.2.4 Temperature Behavior 96
3.2.5 Breakdown Behavior 97
3.3 Second-Order Effects 100
3.3.1 High Current Effects 100
3.3.2 Base-Width Modulation 104
3.3.3 Current Crowding 111
3.4 Alternative Transistor Structures 113
3.5 Modeling the Bipolar Transistor 116
3.5.1 Transistor Model for CAD Applications 117
3.5.2 Transistor Model for Static Calculations 122
3.5.3 Transistor Model for Small-Signal Calculations 122
3.5.4 Transit Time Determination 126
Problems 130
References 134
Further Reading 134
vi CONTENTS
4 MOS Transistor 135
4.1 CMOS Technology 135
4.2 The MOS Structure 141
4.2.1 Characteristic of the MOS Structure 142
4.2.2 Capacitance Behavior of the MOS Structure 145
4.2.3 Flat-Band Voltage 148
4.3 Equations of the MOS Structure 151
4.3.1 Charge Equations of the MOS Structure 151
4.3.2 Surface Voltage at Strong Inversion 155
4.3.3 Threshold Voltage and Body Effect 157
4.4 MOS Transistor 162
4.4.1 Current–Voltage Characteristic at Strong Inversion 162
4.4.2 Improved Transistor Equation 170
4.4.3 Current–Voltage Characteristic at Weak Inversion 171
4.4.4 Temperature Behavior 173
4.5 Second-Order Effects 177
4.5.1 Mobility Degradation 177
4.5.2 Channel Length Modulation 178
4.5.3 Short Channel Effects 180
4.5.4 Hot Electrons 184
4.5.5 Gate-Induced Drain Leakage 185
4.5.6 Breakdown Behavior 188
4.5.7 Latch-up Effect 189
4.6 Power Devices 191
4.7 Modeling of the MOS Transistor 200
4.7.1 Transistor Model for CAD Applications 200
4.7.2 Transistor Model for Static and Dynamic Calculations 208
4.7.3 Transistor Model for Small-Signal Calculations 210
Problems 214
Appendix A Current–Voltage Equation of the MOS Transistor
under Weak Inversion Condition 218
References 223
Further Reading 225
5 Basic Digital CMOS Circuits 227
5.1 Geometric Design Rules 227
5.2 Electrical Design Rules 233
5.3 MOS Inverter 238
5.3.1 Depletion Load Inverter 239
5.3.2 Enhancement Load Inverter 242
5.3.3 PMOS Load Inverter 244
5.3.4 CMOS Inverter 246
5.3.5 Ratioed Design Issues 252
5.4 Switching Performance of the Inverters 254
5.5 Buffer Stages 263
5.5.1 Super Buffer 263
5.5.2 Bootstrap Buffer 267
5.6 Input/Output Stage 269
5.6.1 Input Stage 269
5.6.2 Output Stage 273
5.6.3 ESD Protection 279
Problems 282
References 285
6 Combinational and Sequential CMOS Circuits 287
6.1 Static Combinational Circuits 287
6.1.1 Complementary Circuits 287
6.1.2 PMOS Load Circuits 292
6.1.3 Pass-Transistor Circuits 293
6.2 Clocked Combinational Circuits 296
6.2.1 Clocked CMOS Circuits (C2
MOS) 296
6.2.2 Domino Circuits 298
6.2.3 NORA Circuits 299
6.2.4 Differential Cascaded Voltage Switch Circuits (DCVS) 301
6.2.5 Switching Performance of Ratioless Logic 302
6.3 High Speed Circuits 304
6.4 Logic Arrays 311
6.4.1 Decoder 311
6.4.2 Programmable Logic Array 316
6.5 Sequential Circuits 319
6.5.1 Flip-flop 319
6.5.2 Two-Phase Clocked Register 325
6.5.3 One-Phase Clocked Register 328
6.5.4 Clock Distribution and Generation 332
Problems 334
References 336
Further Reading 336
7 MOS Memories 337
7.1 Read Only Memory 337
7.2 Electrically Programmable and Optically Erasable Memory 339
7.2.1 EPROM Memory Architecture 341
7.2.2 Current Sense Amplifier 343
7.3 Electrically Erasable and Programmable Read Only Memories 345
7.3.1 EEPROM Memory Cells 345
7.3.2 Flash Memory Architectures 352
7.3.3 On-Chip Voltage Generators 357
7.4 Static Memories 362
7.4.1 Static Memory Cells 362
7.4.2 SRAM Memory Architecture 365
7.4.3 Address Transition Detection 367
7.5 Dynamic Memories 369
7.5.1 One-Transistor Cell 369
7.5.2 Basic DRAM Memory Circuits 374
7.5.3 DRAM Architecture 380
7.5.4 Radiation Effects in Memories 383
Problems 385
References 389
Further Reading 390
8 Basic Analog CMOS Circuits 391
8.1 Current Mirror 392
8.1.1 Improved Current Sources 394
8.2 Source Follower 398
8.3 Basic Amplifier Performance 400
8.3.1 Miller Effect 404
8.3.2 Differential Stage with Symmetrical Output 407
8.3.3 Differential Input Stage with Single-Ended Output 411
Problems 417
Appendix A Transfer Functions 418
Further Reading 425
9 CMOS Amplifiers 427
9.1 Miller Amplifier 427
9.2 Folded Cascode Amplifier 438
9.3 Folded Cascode Amplifier with Improved Driving Capability 440
Problems 445
References 446
10 BICMOS 447
10.1 Current Steering Techniques 447
10.1.1 CML Circuits 447
10.1.2 ECL Circuits 454
10.2 BICMOS Buffer and Gates 457
10.3 Band-Gap Reference Circuits 461
10.4 Analog Applications 471
10.4.1 Offset Voltage of Bipolar and MOS Transistors 472
10.4.2 Comparison of Small-Signal Performance 473
Problems 482
References 484
Index 485

附件
System Integration.part1.rar (5 MB)
System Integration.part2.rar (5 MB)
System Integration.part3.rar (4.32 MB)