/*******************************************************************/分频50MHz到2Hz
always @( posedge clk or negedge rst)//分频,50MHz周期为20ns,在12500000*20ns=0.25s clk_div8翻转,即clk_div周期为2*0.25s=0.5s,即2Hz
begin
if(!rst)
begin
clk_cnt <= 1'b0;
clk_1Hz<= 1'b0;
end
else
begin
if(clk_cnt == N-1)
begin
clk_1Hz <= ~clk_1Hz;
clk_cnt <= 1'b0;
end
else
clk_cnt <= clk_cnt + 1'b1;
end
end
/*******************************************************************///增加或者减小频率
always @( k )
begin
if(add==1 & !k) //加快频率
begin
N <= N/2;
end
else if(red==1 & !k) //减慢频率
begin
N <= N*2;
end
else if(k) //恢复初始频率
begin
N <= 12500000;
end
end
管脚约束
NET "add" LOC = G12;
NET "red" LOC = C11;
NET "k" LOC = A7;
NET "clk" LOC = B8;