数据位为48的UART接收器设计VHDL代码ISE仿真

名称：数据位为48的UART接收器设计VHDL代码ISE仿真

软件：ISE

语言：VHDL

代码功能：

数据位为48的UART接收器

1、数据位宽为48位，其中1起始，48数据，1停止位。

2、使用移位寄存器依次接收48位。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.?工程文件

2.?程序文件

3.?程序运行

4.?Testbench

测试文件产生rx信号，按115200的波特率输出（低位在前）10101010101010...这样01交替变换的数据，相当于应该接收到48位的010101010101010...这样的并行数据。新组合的6bit数据应该为111111。

5.?仿真图

Rx交替变换

接收到48位010101010101010...，取第0,8,16,24,32,40位，组成new_data=111111

延迟输出new_data=111111

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?uart_rx_module?IS
???PORT?(
??????
??????clk_100M?????????:?IN?STD_LOGIC;
??????rst_p????????????:?IN?STD_LOGIC;--高电平复位
??????uart_rx??????????:?IN?STD_LOGIC;
data_receive_48??:?OUT?STD_LOGIC_VECTOR(47?DOWNTO?0);
??????data_serial_out??:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0)
???);
END?uart_rx_module;
ARCHITECTURE?trans?OF?uart_rx_module?IS
???
???SIGNAL?bps_cnt????????:?STD_LOGIC_VECTOR(15?DOWNTO?0):=?"0000000000000000";
???SIGNAL?bps_cnt_mid????:?STD_LOGIC_VECTOR(15?DOWNTO?0):=?"0000000000000000";
???
???SIGNAL?rx_mid?????????:?STD_LOGIC?:=?'0';--中间位置采样???????
???SIGNAL?rx_en??????????:?STD_LOGIC?:=?'0';--rx_en是接收数据使能信号
???SIGNAL?cnt????????????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000000000000000";
???SIGNAL?num????????????:?STD_LOGIC_VECTOR(5?DOWNTO?0)?:=?"000000";--num表示对应数据位
???
???SIGNAL?rx_r0??????????:?STD_LOGIC:=?'0';
???SIGNAL?rx_r1??????????:?STD_LOGIC:=?'0';
???
???SIGNAL?rx_req?????????:?STD_LOGIC:=?'0';
???
???SIGNAL?rx_done????????:?STD_LOGIC:=?'0';
???
???SIGNAL?rx_data????????:?STD_LOGIC_VECTOR(47?DOWNTO?0):=?"000000000000000000000000000000000000000000000000";
???
???SIGNAL?receive_data???:?STD_LOGIC_VECTOR(47?DOWNTO?0)?:=?"000000000000000000000000000000000000000000000000";
???
???SIGNAL?receive_data_1?:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?receive_data_2?:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?receive_data_3?:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?receive_data_4?:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?receive_data_5?:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?receive_data_6?:?STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???
???SIGNAL?new_data???????:?STD_LOGIC_VECTOR(5?DOWNTO?0):=?"000000";
???
???SIGNAL?data_count?????:?STD_LOGIC_VECTOR(5?DOWNTO?0)?:=?"000000";
BEGIN
???bps_cnt?<=?"0000001101100011";
???bps_cnt_mid?<=?"0000000110110001";
???PROCESS?(clk_100M,?rst_p)
???BEGIN
??????IF?(rst_p?=?'1')?THEN
?????????rx_mid?<=?'0';
??????ELSIF?(clk_100M'EVENT?AND?clk_100M?=?'1')?THEN
?????????IF?(rx_en?=?'1')?THEN
????????????IF?(cnt?=?bps_cnt_mid)?THEN
???????????????rx_mid?<=?'1';
????????????ELSE
???????????????rx_mid?<=?'0';
????????????END?IF;
?????????ELSE
????????????rx_mid?<=?'0';
?????????END?IF;
??????END?IF;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1146