CDCLVP2102是一款高性能，低附加相位噪声时钟缓冲器。DescriptionThe CDCLVP2102 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, and each input feeds a bank of two LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP2102. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP2102 device functionalities. For optimum performance, the board is equipped with 50-W SMA connectors and well-controlled, 50-W impedance microstrip transmission lines. Features
Easy-to-use evaluation board to fan out low phase noise clocks
Easy device setup
Fast configuration
Control pins configurable through jumpers
Board powered at +2.5-/+3.3-V
Single-ended or differential input clocks
CDCLVP2102 supports four LVPECL outputs; CDCLVP2102EVM supports two LVPECL outputs
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2014-03-21
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