?? ? ? ? ?Responsibilities:
?? ? ? ? ?- Work with algorithm team to come up with the best architecture.
?? ? ? ? ?- Logic design using Verilog or VHDL.
?? ? ? ? ?- Perform block level synthesis and timing check.
?? ? ? ? ?- RTL modeling, simulation and verification
?? ? ? ? ?- Familiar with DFT (design for testing) techniques
?? ? ? ? ?- Power estimation and low power design techniques
?? ? ? ? ?- Excellent communication and presentation skills .
?? ? ? ? ?- Well organized, methodical, and detail oriented
?? ? ? ? ?- Team player and easy to work ?with
?? ? ? ? ?Requirements:
?? ? ? ? ?- MSEE or BSEE required
?? ? ? ? ?- 3+ years experience in communication related fields. ?
?? ? ? ? ?- Strong skills in Verilog RTL design and verification.
?? ? ? ? ?- Familiar with digital signal processing and ?MATLAB are highly desired
?? ? ? ? ? -Strong programming skills in Perl, C, and TCL
#其他
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2007-08-17
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