RAM控制器设计VHDL代码ISE仿真

名称：RAM控制器设计VHDL代码ISE仿真

软件：ISE

语言：VHDL

代码功能：

RAM控制器

1、使用状态机设计RAM控制器；

2、其中状态机编码分别使用二进制编码、独热码、格雷码；

3、使用2种编码风格。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.?工程文件

State编码方式分别为：二进制编码、独热码、格雷码

2.?程序文件

状态机编码方式（下图为二进制编码）

3.?程序编译

资源占用

4.?Testbench

5.?仿真图

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?RAM_Controller_1?IS
???PORT?(
??????clock???????:?IN?STD_LOGIC;
??????cs??????????:?IN?STD_LOGIC;
??????wr??????????:?IN?STD_LOGIC;
??????rd??????????:?IN?STD_LOGIC;
??????addrin??????:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0);
??????ready???????:?OUT?STD_LOGIC;
??????re??????????:?OUT?STD_LOGIC;
??????addrout?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????ras?????????:?OUT?STD_LOGIC;
??????cas?????????:?OUT?STD_LOGIC
???);
END?RAM_Controller_1;
ARCHITECTURE?behave?OF?RAM_Controller_1?IS
???SIGNAL?state?:?STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"000";?
???constant??s_idle??????:STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"000";??
???constant??s_loadaddr??:STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"001";??
???constant??s_wr????????:STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"010";??
???constant??s_rd????????:STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"011";??
???constant??s_ready?????:STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"100";??
???constant??s_ras_addr??:STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"101";??
???constant??s_cas_addr??:STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"110";??
???SIGNAL?wr_r??:?STD_LOGIC;
???SIGNAL?rd_r??:?STD_LOGIC;
BEGIN
--2段式状态机
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN
?????????CASE?state?IS
????????????WHEN?s_idle?=>
???????????????IF?(cs?=?'1')?THEN
??????????????????state?<=?s_loadaddr;
???????????????ELSE
??????????????????state?<=?s_idle;
???????????????END?IF;
????????????WHEN?s_loadaddr?=>
???????????????IF?(wr?=?'1')?THEN
??????????????????state?<=?s_wr;
???????????????ELSIF?(rd?=?'1')?THEN
??????????????????state?<=?s_rd;
???????????????ELSE
??????????????????state?<=?s_loadaddr;
???????????????END?IF;
????????????WHEN?s_wr?=>
???????????????state?<=?s_ready;
????????????WHEN?s_rd?=>
???????????????state?<=?s_ready;
????????????WHEN?s_ready?=>
???????????????state?<=?s_ras_addr;
????????????WHEN?s_ras_addr?=>
???????????????state?<=?s_cas_addr;
????????????WHEN?s_cas_addr?=>
???????????????state?<=?s_idle;
????????????WHEN?OTHERS?=>
?????????END?CASE;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN
?????????IF?(state?=?s_ready)?THEN
????????????ready?<=?'1';
?????????ELSE
????????????ready?<=?'0';
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN
?????????IF?(state?=?s_loadaddr)?THEN
????????????wr_r?<=?wr;
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN
?????????IF?(state?=?s_loadaddr)?THEN
????????????rd_r?<=?rd;
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN
?????????IF?(state?=?s_ras_addr)?THEN
????????????addrout?<=?addrin(15?DOWNTO?8);
?????????ELSIF?(state?=?s_cas_addr)?THEN
????????????addrout?<=?addrin(7?DOWNTO?0);
?????????END?IF;
??????END?IF;
???END?PROCESS;

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