AD7606驱动代码设计VHDL代码Quartus仿真

名称：AD7606驱动代码设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

AD7606B输入

(4800-输入)/8(仿真时=学号后3位),

PWM输出

(600=100%)

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 仿真图

整体仿真图

AD7606模块

计算模块

PWM模块

部分代码展示:

LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_unsigned.all;
--AD7606模块
ENTITY AD7606 IS
   PORT (
      sys_clk       : IN STD_LOGIC;--时钟
      reset     : IN STD_LOGIC;--复位
      RD_n        : OUT STD_LOGIC;--AD引脚
  CONVST   : OUT STD_LOGIC;--AD引脚
      ADRESET   : OUT STD_LOGIC;--AD引脚
      CS_n        : OUT STD_LOGIC;--AD引脚
      BUSY      : IN STD_LOGIC;--AD引脚
      DB_IN   : IN STD_LOGIC_VECTOR(15 DOWNTO 0);--AD值引脚  
      OS        : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);--AD引脚
      DOUT       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)--采样值
   );
END AD7606;
ARCHITECTURE RTL OF AD7606 IS
   SIGNAL AD_state:  STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL div_count  : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL CONVST_signal : STD_LOGIC;
   SIGNAL read_en      : STD_LOGIC;
   SIGNAL RD_END      : STD_LOGIC;
   SIGNAL count       : STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL VIM_CNT        : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
   OS <= "000";
   ADRESET <= NOT reset ;
   
   --AD状态控制
   PROCESS (sys_clk, reset)
   BEGIN
      IF (reset = '0') THEN
         AD_state <= "000";
 div_count <= "00000000";
      ELSIF (sys_clk'EVENT AND sys_clk = '1') THEN
      CASE AD_state IS
         WHEN "000" =>
IF (div_count = "01100100") THEN
div_count <= "00000000";--计数到100
ELSE
div_count <= div_count + "00000001";
END IF;
            IF (div_count = "01100100") THEN---控制采样率，为系统时钟的100分频
               AD_state <= "001";
            END IF;
         WHEN "001" =>
            IF (CONVST_signal = '1') THEN--检测CONVST
               AD_state <= "010";
            END IF;
         WHEN "010" =>
            IF (BUSY= '0') THEN
AD_state <= "011";--检测BUSY
            END IF;
         WHEN "011" =>--读数
            AD_state <= "100";
         WHEN "100" =>
            IF (RD_END = '1') THEN--读完成
               AD_state <= "000";
            END IF;
         WHEN OTHERS =>
            AD_state <= "000";
      END CASE;