AD7706b驱动及PWM波输出设计VHDL代码Quartus仿真

名称：AD7706b驱动及PWM波输出设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

AD7606B输入

(4800-输入)/8(仿真时=学号后3位)

PWM输出

(600=100%)

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

PWM占空比为学号除以600乘以100%

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 仿真图

整体仿真图

AD7606B模块仿真

PWM模块仿真

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--8通道adc7606b的硬件模式，并行输出模式
ENTITY?AD7606B?IS
???PORT?(
??????clk???????:?IN?STD_LOGIC;--时钟
??????rst_n?????:?IN?STD_LOGIC;--复位
??????os????????:?OUT?STD_LOGIC_VECTOR(2?DOWNTO?0);--输出低电平
??????adc_cvt???:?OUT?STD_LOGIC;--convst
??????adc_rst???:?OUT?STD_LOGIC;--高电平复位
??????rd????????:?OUT?STD_LOGIC;--低电平读
??????cs????????:?OUT?STD_LOGIC;--低电平使能
??????busy??????:?IN?STD_LOGIC;--忙
??????ad_data???:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0);--并行输入AD
??????ch1???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出通道1
??????ch2???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出通道2
??????ch3???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出通道3
??????ch4???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出通道4
??????ch5???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出通道5
??????ch6???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出通道6
??????ch7???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出通道7
??????ch8???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)?--输出通道8
???);
END?AD7606B;
ARCHITECTURE?behave?OF?AD7606B?IS
???type?state?is?(
??????IDLE??????,
??????CVT???????,
??????BUSY_S??????,
??????RD_ST?????,
??????GET_DATA??
???);
???SIGNAL?state_c???????:?state;
???SIGNAL?flag??????????:?STD_LOGIC;
???
???SIGNAL?state_n???????:?state;
???SIGNAL?get_data_en???:?STD_LOGIC;
???
???SIGNAL?cnt_mum???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?cnt_cvt???????:?STD_LOGIC_VECTOR(1?DOWNTO?0);
???SIGNAL?cnt_ch????????:?STD_LOGIC_VECTOR(2?DOWNTO?0);
???SIGNAL?adc_cvt_buf?:?STD_LOGIC;
???SIGNAL?rd_buf??????:?STD_LOGIC;
BEGIN
???adc_cvt?<=?adc_cvt_buf;
???rd?<=?rd_buf;
???
???os?<=?"000";--输出0
???adc_rst?<=?NOT(rst_n);--取反
???get_data_en?<=?'1'?when?(cnt_mum?=?"11111001")?else?'0';--采样使能
???
--计数250
???PROCESS?(clk,?rst_n)
???BEGIN
??????IF?((NOT(rst_n))?=?'1')?THEN
?????????cnt_mum?<=?"00000000";
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(cnt_mum?=?"11111001")?THEN
????????????cnt_mum?<=?"00000000";--计数到11111001=249
?????????ELSE
????????????cnt_mum?<=?cnt_mum?+?"00000001";--计数
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???--状态跳转
???PROCESS?(clk,?rst_n)
???BEGIN
??????IF?((NOT(rst_n))?=?'1')?THEN
?????????state_c?<=?IDLE;
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????state_c?<=?state_n;
??????END?IF;
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1029