AD7321和DAC0832驱动VHDL代码Quartus仿真

名称：AD7321和DAC0832驱动VHDL代码Quartus仿真

软件：Quartus

语言：Verilog

代码功能：AD7321和DAC0832驱动VHDL代码

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 仿真文件（vwf文件）

6. 仿真图

部分代码展示:

library?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--AD7321控制模块
ENTITY?AD7321?IS
???PORT?(
??????clk????????:?IN?STD_LOGIC;
??????AD_CS????????:?OUT?STD_LOGIC;--AD信号
??????AD_DOUT????????:?IN?STD_LOGIC;--AD信号
??????AD_SCLK????????:?OUT?STD_LOGIC;--AD信号
??????AD_DIN????????:?OUT?STD_LOGIC;--AD信号
??????AD_data???:?OUT?STD_LOGIC_VECTOR(11?DOWNTO?0)--AD7321采样值
???);
END?AD7321;
ARCHITECTURE?behave?OF?AD7321?IS
???SIGNAL?AD7321_data?:?STD_LOGIC_VECTOR(14?DOWNTO?0):="000000000000000";
???SIGNAL?state???:?STD_LOGIC_VECTOR(1?DOWNTO?0)?:=?"00";
???SIGNAL?SCLK_buf?:?STD_LOGIC?:=?'0';
SIGNAL?AD_data_buf?:?STD_LOGIC_VECTOR(11?DOWNTO?0);
BEGIN
???--状态机控制AD7321时序
???PROCESS?(clk)
???variable?CS_cnt:integer:=?0;
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????CASE?state?IS
????????????WHEN?"01"?=>--CS状态
???CS_cnt:=CS_cnt+1;
???????????????IF?(CS_cnt?>=?10)?THEN--CS状态程序10周期
??????????????????state?<=?"10";
???????????????ELSE
??????????????????state?<=?"01";
???????????????END?IF;
IF?(CS_cnt>2)?THEN
AD_CS?<=?'1';--输出CS高电平,否则低电平
ELSE
AD_CS?<=?'0';
END?IF;
????????????WHEN?"10"?=>--clear
????CS_cnt:=0;
????????????????state?<=?"11";
AD_CS?<=?'0';
????????????WHEN?"11"?=>--SCK状态
??????CS_cnt:=CS_cnt+1;
???????????????IF?(CS_cnt?>=?31)?THEN--SCK状态持续32周期
??????????????????state?<=?"00";
???????????????ELSE
??????????????????state?<=?"11";
???????????????END?IF;
????????????WHEN?"00"?=>--采样结束
??????CS_cnt:=0;
???????????????state?<=?"01";
????????????WHEN?OTHERS?=>
?????????END?CASE;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(state?=?"11")?THEN--SCK状态
????????????SCLK_buf?<=?NOT?SCLK_buf;--产生SCLK_buf，取反，32周期变为16个时钟
?????????ELSE
????????????SCLK_buf?<=?'1';
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???--SCLK_buf上升沿读取SDO的值
???PROCESS?(SCLK_buf)
???BEGIN
??????IF?(SCLK_buf'EVENT?AND?SCLK_buf?=?'1')?THEN
??????????AD7321_data?<=?AD7321_data(13?DOWNTO?0)?&?AD_DOUT;--SCLK_buf上升沿读取AD_DOUT的值放入最低位
END?IF;?
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=917