ADS8364及AD5758芯片驱动设计VHDL代码Quartus仿真

名称：ADS8364及AD5758芯片驱动设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

ADS8364及AD5758芯片驱动设计

本设计的要求如下：ADS8364输入，（5400-输入）9 (仿真时=学号后3位)，AD5758输出。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.工程文件

2.程序文件

3.程序编译

资源消耗

系统主频：50MHz

电路功耗：58.83mW

4.RTL图

5.管脚分配（约束）

6.仿真图

乘法器仿真

Testbench(仿真脚本)

仿真图

十六机制显示

十进制显示

串口收发仿真

Testbench(仿真脚本)

仿真图

数据处理模块仿真

Testbench(仿真脚本)

仿真图

十六进制显示

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--AD5758控制模块
ENTITY?AD5758?IS
???PORT?(
??????clk_da??????:?IN?STD_LOGIC;
??????rst_n???????:?IN?STD_LOGIC;
??????data????????:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0);--AD5758输入数字量
??????ad1?????????:?OUT?STD_LOGIC;--AD5758端口
??????ad0?????????:?OUT?STD_LOGIC;--AD5758端口
??????da_reset_n??:?OUT?STD_LOGIC;--AD5758端口
??????da_ldac_n???:?OUT?STD_LOGIC;--AD5758端口
??????da_sync_n???:?OUT?STD_LOGIC;--AD5758端口
??????da_sclk?????:?OUT?STD_LOGIC;--AD5758端口
??????da_sdi??????:?OUT?STD_LOGIC?--AD5758端口
???);
END?AD5758;
ARCHITECTURE?RTL?OF?AD5758?IS
???type?state_type?is(??
??????s_reset?????,
??????s_wait??????,
??????s_sync??????,
??????s_stop??????
???);
???SIGNAL?state????:?state_type;
???SIGNAL?crc??????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?da_data??:?STD_LOGIC_VECTOR(31?DOWNTO?0);
???
???SIGNAL?wait_cnt?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?sync_cnt?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?stop_cnt?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?crc_reg_d?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?crc_reg_q?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
BEGIN
--输出定值
???da_ldac_n?<=?'0';
???ad1?<=?'0';
???ad0?<=?'0';
--状态机控制
???PROCESS?(clk_da,?rst_n)
???BEGIN
??????IF?((NOT(rst_n))?=?'1')?THEN
?????????state?<=?s_reset;
??????ELSIF?(clk_da'EVENT?AND?clk_da?=?'1')?THEN
?????????CASE?state?IS
????????????WHEN?s_reset?=>
???????????????state?<=?s_wait;
????????????WHEN?s_wait?=>
???????????????IF?(wait_cnt?>?"00110010")?THEN
??????????????????state?<=?s_sync;
???????????????END?IF;
????????????WHEN?s_sync?=>
???????????????IF?(sync_cnt?>?"00100000")?THEN
??????????????????state?<=?s_stop;
???????????????END?IF;
????????????WHEN?s_stop?=>
???????????????IF?(stop_cnt?>?"00001010")?THEN
??????????????????state?<=?s_sync;
???????????????END?IF;
????????????WHEN?OTHERS?=>
???????????????state?<=?s_wait;
?????????END?CASE;
??????END?IF;
???END?PROCESS;
???
???--等待计时
???PROCESS?(clk_da,?rst_n)
???BEGIN
??????IF?((NOT(rst_n))?=?'1')?THEN
?????????wait_cnt?<=?"00000000";
??????ELSIF?(clk_da'EVENT?AND?clk_da?=?'1')?THEN
?????????IF?(state?=?s_wait)?THEN
????????????wait_cnt?<=?wait_cnt?+?"00000001";
?????????ELSE
????????????wait_cnt?<=?"00000000";
?????????END?IF;
??????END?IF;
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1086